» » Image Sensors at 2018 VLSI Symposium

Image Sensors at 2018 VLSI Symposium

VLSI Symposium to be held on June 18-22, 2018 in Honolulu, HI, publishes lists circuits and technology accepted papers with few image sensor related ones:
  • A Two‐Tap NIR Lock‐In Pixel CMOS Image Sensor with Background Light Cancelling Capability for Non-Contact Heart Rate Detection,
    Chen Cao, Shizuoka University
  • A 252 × 144 SPAD pixel FLASH LiDAR with 1728 Dual‐clock 48.8 ps TDCs, Integrated Histogramming and 14.9‐to‐1 Compression in 180nm CMOS Technology,
    Scott Lindner, EPFL and University of Zurich
  • A 220 m‐Range Direct Time‐of‐Flight 688 × 384 CMOS Image Sensor with Sub‐Photon Signal Extraction (SPSE) Pixels Using Vertical Avalanche Photo‐Diodes and 6 kHz Light Pulse Counters,
    Shinzo Koyama, Panasonic Corp.
  • An over 120 dB wide‐dynamic‐range 3.0 μm pixel image sensor with in‐pixel capacitor of 41.7 fF/um2 and high reliability enabled by BEOL 3D capacitor process,
    Masayuki Takase, Panasonic Corporation
  • Next‐generation Fundus Camera with Full Color Image Acquisition in 0‐lx Visible Light by 1.12‐micron Square Pixel, 4K, 30‐fps BSI CMOS Image Sensor with Advanced NIR Multi‐spectral Imaging System,
    Hirofumi Sumi, The University of Tokyo
  • A Near‐ & Short‐Wave IR Tunable InGaAs Nanomembrane PhotoFET on Flexible Substrate for Lightweight and Wide‐Angle Imaging Applications,
    Yida Li, National University of Singapore


0 Response to "Image Sensors at 2018 VLSI Symposium"

Post a Comment

Subscribe to: Post Comments (Atom)