The reduction ideas are not very practical in image sensor usage context, but the authors predicts that the carrier trap-based RTN and 1/f noise will become less common when the transistor dimensions scale down to 10s of nanometers. However, the 1/f noise still stays in the form of a gate dielectric polarization noise, even in very small mosfets. High-K dielectrics have this noise reduced, to a degree.
"While the actual transistor gates in processors reach the sub-10 nm range for optimum integration and power consumption, studies on design rules for the signal-to-noise ratio (S/N) optimization in transistor-based biosensors have been so far restricted to 1 µm2 device gate area, a range where the discrete nature of the defects can be neglected. In this study, which combines experiments and theoretical analysis at both numerical and analytical levels, we extend such investigation to the nanometer range and highlight the effect of doping type as well as the noise suppression opportunities offered at this scale. In particular, we show that, when a single trap is active near the conductive channel, the noise can be suppressed even beyond the thermal limit by monitoring the trap occupancy probability in an approach analog to the stochastic resonance effect used in biological systems."
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