Until now, increasing the number of pixels has resulted in the downside of increased chip and camera size. However, if the pixel size is reduced to prevent increasing the camera size, then the light-accumulating area per pixel will correspondingly decrease, resulting in a drop in the sensitivity and saturation signal level. This results in image quality degradation, in turn leading to degradation in recognition and detection performance.
The proprietary BSI pixel allows for a compact size of only 2.74µm square, which is about 63% of the conventional Sony pixel area, but still maintaining pixel characteristics such as sensitivity and saturation signal level. While using the same optical system as previous models, the number of pixels has been increased and the package size (area) has been reduced to about 91%.
The new products achieve a readout frame rate approximately 2.4 times the speed of conventional Sony image sensors thanks to the highly flexible wiring layout of the BSI pixel structure, and the use of the Scalable Low Voltage Signaling with Embedded Clock (SLVS-EC) high-speed interface standard developed by Sony. Further, the stacked structure allows for embedding various signal processing circuits such as HDR processing circuit that can prevent distortion in moving objects, thereby enabling myriad functions for various machine vision applications in a package more compact than conventional image sensors.
The Pregius S lineup includes the high-speed IMX530/531/532 models for high-end cameras using high-speed bandwidth, in addition to the standard IMX540/541/542 models that support 5Gbps supplementing the expansion in the application of USB 3.0 and 5GigE.
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