"In the context of High Definition imagers, a trend is to integrate a bank of analogto-digital converters adjacent to the pixel matrix. The disadvantage is a constraint on the form factor of the converter. An incremental inverter-based Sigma-Delta converter was designed during previous work while respecting these constraints. But the post-layout of the circuit resulted in a performance degradation namely a resolution of 9 bits instead of the expected 14 bits. A calibration method was therefore necessary. This thesis proposes several correction methods implemented by digital filters applied on the output bits and on combinations of the output bits to take account of non-linear phenomena observed in post-layout simulation. The methods have been validated from the post-layout simulation results and achieve 14-bit resolution. To go further, the thesis also proposes a model of the circuit defects at the level of the integrators which are the most critical part of the circuit. This model, which implements parasitic capacitances, joins the post-layout simulation results with a very high precision, which makes it possible to consider ways of improvement for a future design."
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